module tb_flipflop;
    
    reg clk,rst;
    reg[1:0] data_in;
    wire[1:0] data_out;
    
    initial
    begin
        clk = 0;
        rst = 1;
        data_in = 0;
        #5 rst = 0;
        #5 rst = 1;
    end
    
    always #10 clk = ~clk;
    always #20 data_in = data_in + 1;
    
    flipflop flipflop1(
                        .clk(clk), 
                        .rst(rst), 
                        .data_in(data_in), 
                        .data_out(data_out)
                        );

endmodule