module shifter(clk ,rst, in_a, in_b, out);
    
    input clk, rst;
    input [1:0]in_a, in_b;
    output[1:0] out;
    
    reg[1:0] out;
    
    always@(posedge clk or negedge rst)
    if(rst == 0) out = 0;
    else if(in_b == 1)  out = in_a<<1;
    else if(in_b == 2)  out = in_a<<2;
    else out = in_a;
    
endmodule

