module flipflop (clk, rst, data_in, data_out);
    
    input clk, rst;
    input[1:0] data_in;
    output[1:0] data_out;
    
    reg[1:0] data_out;
    reg[1:0] data_ff[1:0];
    
    always@(posedge clk or negedge rst)
    if(!rst)
    data_out <= 0;
    else 
    begin
        data_ff[0] <= data_in;
        data_ff[1] <= data_ff[0];
        data_out <= data_ff[1];
    end
    
endmodule
