module adder(clk ,rst, in_a, in_b, out);
    
    input clk, rst;
    input in_a, in_b;
    output[1:0] out;
    
    reg[1:0] out;
    
    always@(posedge clk or negedge rst)
    if(rst == 0) out = 0;
    else out = in_a + in_b;
    
endmodule
