module case (clk ,rst, in_a, in_b, out);
    
    input clk, rst;
    input [1:0] in_a, in_b;
    output[1:0] out;
    
    reg[1:0] out;
    
    always@(posedge clk or negedge rst)
    begin
     case(in_b)
	1 : out = in_a<<1;
	2 : out = in_a<<2;
	3 : out = in_a;
	default : out = 0;
     endcase
    end

endmodule

