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´ÙÃþ ¹Ý»ç ±â¹ýÀ» ÅëÇÑ ÀÔü Ȧ·Î±×·½ ½Ã½ºÅÛ (Three dimensional hologram system using multiple reflection layer methodologies)

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°í¼Ó Àú Àü¿ø ³ëÀÌÁî Display Panel Driver ¼³°è (High speed low noise Display Panel Driver design)

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µð½ºÇ÷¹ÀÌ ÆгÎÀ» À§ÇÑ Backlight Á¦¾î ¹æ¹ý°ú Discrete Cosine Transform ¼³°è ¹æ¾È (Methodologies for Backlight control and Discrete Cosine Transform for Display panel)

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±¤¿ª ¿µ»ó °¨½Ã ½Ã½ºÅÛÀ» À§ÇÑ »óȲ¿¡ µû¸¥ ¾ÇõÈÄ ¿µ»ó È­Áú °³¼±°ú ÀÎ½Ä ±â¼ú ¹× Á¤¹Ð ±¸µ¿Ã¼ ½Ã½ºÅÛ °³¹ß (Development of bad weather image quality enhancement, recognition and precision actuator system for long distance image surveillance)

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¾ÇõÈÄ ¿µ»ó È­Áú Çâ»ó ¹× ¿µ»ó µ¥ÀÌÅÍ ¾ÐÃà ¾Ë°í¸®Áò°ú ¾ÆÅ°ÅØÃÄ (Algorithm and architecture for bad weather image quality enhancement and image data compression)

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LCD backlight dimming°ú ´Ù¾çÇÑ ÁöÇ¥ Á¶ÀýÀ» ÅëÇÑ È­Áú Çâ»ó ¹æ¾È (Image quality enhancement based on LCD backlight dimming and various image metric optimizations)

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È¿À²ÀûÀÎ BLU dimming°ú ±ÔÄ¢ÀûÀÎ DCT/IDCT CodecÀ» ÅëÇÑ °íÈ­Áú, ÀúÀü·Â Display System on Panel ¼³°è ¹æ¾È (High image quality, low power Display System on Panel design with efficient BLU dimming and regular DCT/IDCT Codec)

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ÃÖÀû È­ÁúÀ» À§ÇÑ ¹é¶óÀÌÆ® À¯´ÖÀÇ LED ¼³°è ¹æ¾È (Backlight unit LED design for optimum image quality)

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È­Áú Çâ»óÀ» À§ÇÑ LCD BLUÀÇ È¿À²ÀûÀÎ Á¦¾î ¹æ¾È °³¹ß (Efficient LCD BLU control methodologies for image enhancement)

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Display Panel È­Áú Çâ»óÀ» À§ÇÑ ¿¬»ê ó¸® ¾Ë°í¸®Áò °³¹ß (Arithmetic algorithm development for display panel image enhancement)

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System on Panel¿¡ ÀûÇÕÇÑ Fault tolerant Data Management Unit ¹× Parallel Built in Self Testable Image Compression Memory (Fault tolerant Data Management Unit and Parallel Built in Self Testable Image Compression Memory for System on Panel)

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DCT, Coprocessor, DMU, Parallel BIST Image Buffer·Î ±¸¼ºµÈ System on Panel(SOP) Platform ¼³°è ¹æ¾È (System on Panel (SOP) Platform Design Methodologies with DCT, Coprocessor, DMU and Parallel BIST Image Buffer)

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Data Manipulation ¹× Fault Tolerant DCT¸¦ ÀÌ¿ëÇÑ SOP È­»ó ¸Þ¸ð¸®ÀÇ È¿À²Àû ÀúÀå¹æ¾È (An Efficient SOP frame memory storage methodology using data manipulation and fault tolerant DCT)

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LTPS TFT¸¦ ÀÌ¿ëÇÑ È­¼Ò, ±¸µ¿È¸·Î, ½Ã½ºÅÛ¿ë °¢Á¾ ȸ·Î ¼³°è ±â¹Ý±â¼ú °³¹ß (Circuit design technologies for LTPS TFT pixel driving system)

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À¯ºñÄõÅͽº ¹«¼± ³×Æ®¿öÅ© ½Ã½ºÅÛ °³¹ß ½Ç¹«´É·Â ¹è¾çÀ» À§ÇÑ ±³Àç ¹× ±³À°¹æ¹ý °³¹ß (Development of curriculum and teaching methodology for improving practical design techniques on ubiquitous wireless network systems)

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TFT-LCD Display PanelÀ» À§ÇÑ SOP Processor Scaling ¹æ¾È (Processor Scaling methodologies for TFT-LCD Display Panel SOP)

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Â÷¼¼´ë °¨¼ºÇü µðÁöÅÐ Á¤º¸ µð½ºÇ÷¹ÀÌ Çõ½Å Ŭ·¯½ºÅÍ ±¸Ãà(Á¤º¸µð½ºÇ÷¹ÀÌ °¨¼ºÈ­Áú ±¸Çö Çϵå¿þ¾î ºÐ¾ß) (Cluster for Advanced Information Displays with Enhanced Human Sensibility Ergonomics)

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Coprocessor Fault Detection Routine À» ÅëÇÑ È¿À²ÀûÀÎ Redundancy Replacement ¹æ¾È (Efficient Methodology for Redundancy Replacement with Coprocessor Fault Detection Routine)

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ITÇаú ±³°ú°úÁ¤ °³ÆíÁö¿ø»ç¾÷ (IT curriculum reform support project)

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ÀüÀÚÀü±â°øÇкΠ±âÃÊ-÷´Ü ºÐ¾ß ¿¬°è¸¦ À§ÇÑ ½Å±Ô±³°ú¸ñ ¹× ±³¼ö-ÇнÀ ¹æ¹ý °³¹ß (Electronic and Electrical Engineering – basis-the new curriculum and teaching for the high-tech association-learning development)

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TFT-based ½Ã½ºÅÛ architecture ¹× fault-tolerant processor ¼³°è±â¼ú °³¹ß (Design Technology Development of TFT-based system Architecture and Fault-tolerant processor)

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Faulty Bit ÃßÀûÀÌ ¿ëÀÌÇÑ °íÁýÀû DRAM BIST ¼³°è (Design of high density DRAM BIST with easy location of faulty bits)

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CMOS À̵¿Åë½Å Transceiver Ĩ ¹× ½Ã½ºÅÛ ¼³°è (CMOS mobile communication transceiver chip and system)

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Multimedia coprocessorÀÇ È¿À²ÀûÀÎ interface ¹× Á¦¾î¹æ¾È (Optimal control and interface methodologies for multimedia coprocessor)

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°í¼Ó È­»ó󸮿¡ ¿ì¼öÇÑ general purpose signal processor (Design of Signal processor execution unit in excellent picture and sound information processing)

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Shape adaptive ÀÌ»ê ¿©Çö º¯È¯ VLSI ±¸Çö ¹æ¾È (Shape adaptive Discrete Cosine Transform VLSI implementation)

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°èÃþ±¸Á¶ Ž»ö ¾Ë°í¸®ÁòÀ» ÀÌ¿ëÇÑ ¿òÁ÷ÀÓ ÃßÁ¤ ÇÁ·Î¼¼¼­ÀÇ VLSI ¾ÆÅ°ÅØÃÄ ¼³°è ¹× ±¸Çö¹æ¾È ¿¬±¸ (VLSI Architecture Design and Implementation Study of the motion estimation processor using a hierarchical search algorithm)

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ÇÁ·Î¼¼¼­ ¸ðµ¨¸µ ¹× °ËÁõ±â¼ú ¿¬±¸ (Custom ¼³°è ºÐ¾ß) (Processor modeling and verification technology research (Custom Design Areas))

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Ư¼ö DSP ±â´Éºí·°°³¹ß ¹× ¶óÀ̺귯¸® ±¸Ãà (¿òÁ÷ÀÓ ÃßÁ¤ Çϵå¿þ¾î ±â´É ºí·° ¹× ¶óÀ̺귯¸® °³¹ß) (Specially developed DSP function blocks and libraries (Motion estimation hardware function block library and development)

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VLSI ±¸ÇöÀ» À§ÇÑ Motion Estimation ¾Ë°í¸®ÁòÀÇ ºñ±³ºÐ¼® (Comparison of Motion Estimation Algorithm for VLSI Implemention)

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°í¼Ó È­»ó 󸮿¡ ¿ì¼öÇÑ general purpose signal processorÀÇ »óÀ§·¹º§ ¼³°è (High-level design of the superior general purpose signal processor for high-speed image processing)

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¼¿ ¶óÀ̺귯¸® º¸¿Ï ¹× Á¤¼ö¿¬»êÀåÄ¡ µ¥ÀÌŸÆнº ¼³°è (Cell libraries complement and integer arithmetic unit data path design)

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Constant Geometry Discrete Cosine Transform ÇÁ·Î¼¼¼­¸¦ À§ÇÑ VLSI ¾Ë°í¸®Áò  (VLSI Algorithm and Architecture for Constant Geometry Discrete Cosine Transform)

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°í¼Ó È­»ó󸮿¡ ¿ì¼öÇÑ general purpose signal processor (High-level synthesis of high speed general purpose)

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Fractional-pel Á¤È®µµ¸¦ °®µµ·Ï È®Àå °¡´ÉÇÑ ¿òÁ÷ÀÓ º¸»ó ÇÁ·Î¼¼¼­ÀÇ VLSI ¼³°è

(Fractional-pel accuracy motion compensation have scalable processor VLSI Design)

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¼¿ ¶óÀ̺귯¸® ±¸Ãà¿¡ °üÇÑ ¿¬±¸ (Study on cell library building)

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16-bit Microcontroller ¼³°è (16-bit Microcontroller design)

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°í¼Ó ½Ç½Ã°£ ó¸® full Search Block matching ¿òÁ÷ÀÓ ¹æ½Ä VLSI ÇÁ·Î¼¼¼­ ¼³°è (The design of real-time high speed full search block matching VLSI Motion compensation processor)

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ÀÌÂ÷¿ø constant geometry FFT processing element chip ±¸Çö (Implementation of a two - dimensional constant geometry FFT processing element chip)

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HDTV¿ë Motion compensationÀ» À§ÇÑ VLSI ¾ÆÅ°ÅØÃÄ (VLSI Architecture and Circuit Design for HDTV)

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µðÁöÅÐ À̵¿Åë½Å¿ë À½¼ººÎȣȭ ¹æ½Ä¿¡ °üÇÑ ¿¬±¸ (Study on the digital audio encoding system for mobile communication)

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FFT ÇÁ·Î¼¼¼­¸¦ À§ÇÑ VLSI ¾Ë°í¸®Áò°ú ¾ÆÅ°ÅØÃÄ (VLSI algorithm and architecture for the FFT processor)

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°í¼±¸í TV ºÎȣȭ¸¦ À§ÇÑ ½Ã½ºÅÛ ±¸Çö ¹æ¾È ¿¬±¸ (Implementation Study for encoding high-definition TV)

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Constant Geometry 2-D FFT¸¦ À§ÇÑ VLSI ¾Ë°í¸®ÁòÀÇ °³¹ß°ú ¾ÆÅ°ÅØÃÄÀÇ ±¸Çö (VLSI algorithm and architecture development for Constant Geometry 2-D FFT))

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°í¼Ó (High band width) DRAMÀÇ ±¸Á¶ ¹× ÄÁÆ®·Ñ·¯ ¼³°è (The structure and design of high-speed cntroller (High band width) DRAM)